EDN

Testing and Debugging DSP Systems, Part 1

Part two explains the workings of the JTAG (IEEE 1149.1) boundary-scan technology. In software development, perhaps the most critical, yet least predictable stage in the process is debugging. Many ...
EDN

JTAG 101 – Part 1: Overview and On-Chip Debug Methods

JTAG (jay-tag) is one of the engineering acronyms that has been transformed into a noun, although arguably it is not so popular as RAM, or CPU. IEEE Std 1149.1-1990 IEEE Standard Test Access Port and ...
Embedded

Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1

Enabling a robust on-chip debug capability is being recognized as animportant Design for Debug (DFD) capability for complex SoC and having DFDstandardization makes the Open Core Protocol (OCP) ...
Design-Reuse

Techniques for debugging an asymmetric multi-core application: Part 2

In Part 1 in this series, we covered what an asymmetric multi-core application is, and what are the typical problems that can be encountered in such a system. Now that we have an understanding of ...
Electronic Design

Hardware Emulation for Software Validation (Part 2): Hybrid Emulation and Trace-Based Debug (.PDF Download)

Hardware emulation continues to prove itself as a handy tool for hardware/software co-verification, where the objective is testing the integration of hardware and software. Part 1 of this series ...